Real-Time Federated Learning at the Wireless Edge via Algorithm-Hardware Co-Design (EP/X019160/1)

About this project

This project is supported by EPSRC (EP/X019160/1) under the EPSRC New Horizon Programme and in partner with the University of Exeter.

This project will create revolutionary algorithm-hardware co-design approaches to make FL a real-time process with unparalleled speed, performance, and energy-efficiency at the wireless edge, capable of meeting the stringent requirements of mission-critical applications. This research will pioneer a set of original methods and innovative technologies including: 1) disruptive lightweight hardware-aware FL algorithms that significantly reduce communication, computing, and energy costs while achieving fast model updates; 2) rigorous mathematical analyses of the proposed algorithms to prove their convergence rates and offer theoretical insights into how they perform under various edge network conditions; 3) an automatic hardware-software co-optimisation framework integrating specialised training-acceleration and power-reduction methods to realise optimised, energy-efficient hardware acceleration; and 4) a unique prototype system that will integrate the designed FL hardware accelerator and real-time FL algorithms and be evaluated in a realistic wireless edge networking testbed


  • 09/2022: the grant application has been accepted by the EPSRC New Horizon scheme.