About this project
This project is supported by EPSRC (EP/V034111/1), and we are investigating different hardware architectures for accelerating various deep learning (DL) algorithms using adaptive hardware acceleration platforms. This project proposes to design a new flexible hardware architecture to enable adaptive support for a variety of DL algorithms on embedded devices. To produce lower cost, lower power and higher processing efficiency DL-inference hardware that can be dynamically configured for dedicated application specifications and operating environments, this will require radical innovation in the optimisation of network architecture, software and hardware of current DL techniques.
- We are participating Xilinx adaptive computing challenge 2020:, and we have won a Zynq® UltraScale+™ MPSoC ZCU104 Evaluation Kit
- Project details can be found from here at hackster.io
- 04/2022: Our submission All-in-one Self-adaptive Computing Platform for Smart City to Adaptive Computing Challenge 2021 with Xilinx, has been awarded for the best project for Xilinx University Program (XUP).
- 09/2021: we are participating Adaptive Computing Challenge 2021 with Xilinx
- 09/2021: Our paper “FPGA based Adaptive Hardware Acceleration for Multiple Deep Learning Tasks” has been accepted as a REGULAR paper for presentation at the 14th IEEE MCSoC 2021 and publication in IEEE CPS proceedings
- 08/2021: we are participating LOW-POWER COMPUTER VISION CHALLENGE 2021 (FPGA Detection Track)